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» Time Management in the DoD High Level Architecture
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PPOPP
2005
ACM
15 years 3 months ago
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...
IEEEARES
2006
IEEE
15 years 3 months ago
Application of the Digraph Method in System Fault Diagnostics
There is an increasing demand for highly reliable systems in the safety conscious climate of today’s world. When a fault does occur there are two desirable outcomes. Firstly, de...
E. M. Kelly, L. M. Bartlett
BIS
2009
168views Business» more  BIS 2009»
14 years 10 months ago
Defining Adaptation Constraints for Business Process Variants
Abstract. In current dynamic business environment, it has been argued that certain characteristics of ad-hocism in business processes are desirable. Such business processes typical...
Ruopeng Lu, Shazia Wasim Sadiq, Guido Governatori,...
63
Voted
DAC
2006
ACM
15 years 10 months ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
15 years 6 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras