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» Time Management in the DoD High Level Architecture
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ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
14 years 11 months ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 6 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
66
Voted
DAC
2007
ACM
15 years 10 months ago
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
Khaled R. Heloue, Navid Azizi, Farid N. Najm
ADC
2008
Springer
153views Database» more  ADC 2008»
14 years 11 months ago
A Confidence Based Recognition System for TV Commercial Extraction
Automatic real-time recognition of TV commercials is an essential step for TV broadcast monitoring. It comprises two basic tasks: rapid detection of known commercials that are sto...
Yijun Li, Dianqing Zhang, Xiangmin Zhou, Jesse S. ...
88
Voted
BNCOD
2007
96views Database» more  BNCOD 2007»
14 years 11 months ago
Extracting Temporal Information from Short Messages
Abstract. Information Extraction, the process of eliciting data from natural language documents, usually relies on the ability to parse the document and then to detect the meaning ...
Richard Cooper, Sinclair Manson