658 search results - page 9 / 132 » Time Management in the DoD High Level Architecture |
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
SIGMOD
1991
ACM
15 years 1 months ago
1991
ACM
This paper presents an architecture for a persistent object store in which multi-level storage is explicitly included. Traditionally, DBMSs have assumed that all accessible data r...
ICCD
2005
IEEE
15 years 3 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
IM
2003
14 years 11 months ago
2003
: Quantitative models are needed for a variety of management tasks, including (a) identification of critical variables to use for health monitoring, (b) anticipating service level...
102
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ISORC
2009
IEEE
15 years 4 months ago
2009
IEEE
AUTOSAR as specified in its current version fosters timing-constraints at application level to support the development of real-time automotive applications. However, the standard...