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FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
15 years 5 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
RTAS
2006
IEEE
15 years 5 months ago
Switch Scheduling and Network Design for Real-Time Systems
The rapid need for high bandwidth and low latency communication in distributed real-time systems is driving system architects towards high-speed switches developed for high volume...
Sathish Gopalakrishnan, Marco Caccamo, Lui Sha
INFOCOM
1998
IEEE
15 years 4 months ago
Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
Donpaul C. Stephens, Hui Zhang
NOCS
2010
IEEE
14 years 9 months ago
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
Tushar N. K. Jain, Paul V. Gratz, Alexander Sprint...
CORR
2004
Springer
148views Education» more  CORR 2004»
14 years 11 months ago
Supporting Bandwidth Guarantee and Mobility for Real-Time Applications on Wireless LANs
The proliferation of IEEE 802.11-based wireless LANs opens up avenues for creation of several tetherless and mobility oriented services. Most of these services, like voice over WL...
Srikant Sharma, Kartik Gopalan, Ningning Zhu, Gang...