1449 search results - page 98 / 290 » Time Synchronization |
FPGA
2010
ACM
15 years 5 months ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
ECOOP
2007
Springer
15 years 3 months ago
2007
Springer
UML class diagrams are usually annotated with OCL expressions that constrain their possible instantiation. In our work we have investigated how OCL annotations can be automatically...
DAC
2009
ACM
16 years 6 days ago
2009
ACM
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
HICSS
1996
IEEE
15 years 3 months ago
1996
IEEE
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulati...
EUROMICRO
2004
IEEE
15 years 2 months ago
2004
IEEE
This paper addresses the prediction of timing properties of a component-based application already during the composition phase. At this stage, it is of vital importance to guarant...