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» Time and area efficient pattern matching on FPGAs
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FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
14 years 11 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang
VLSID
2008
IEEE
133views VLSI» more  VLSID 2008»
15 years 9 months ago
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
Today's customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significa...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul
94
Voted
IVS
2008
145views more  IVS 2008»
14 years 9 months ago
Towards a taxonomy of movement patterns
A review of research that has been carried out on data mining and visual analysis of movement patterns suggests that there is little agreement on the relevant types of movement pa...
Somayeh Dodge, Robert Weibel, Anna-Katharina Laute...
CONSTRAINTS
2007
112views more  CONSTRAINTS 2007»
14 years 9 months ago
Maxx: Test Pattern Optimisation with Local Search Over an Extended Logic
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
Francisco Azevedo
72
Voted
DAC
2005
ACM
15 years 10 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He