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» Time in Connectionist Models

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ICCAD
2001
IEEE

104views Hardware» more ICCAD 2001»

A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells

15 years 6 months ago

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We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...

Clayton B. McDonald, Randal E. Bryant

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FUIN
2010

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Bounded Parametric Verification for Distributed Time Petri Nets with Discrete-Time Semantics

14 years 7 months ago

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Bounded Model Checking (BMC) is an efficient technique applicable to verification of temporal properties of (timed) distributed systems. In this paper we show for the first time ho...

Michal Knapik, Wojciech Penczek, Maciej Szreter, A...

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DSRT
2006
IEEE

98views Modeling and Simulation» more DSRT 2006»

Scheduling Hard-Real-Time Tasks with Backup Phasing Delay

15 years 4 months ago