518 search results - page 59 / 104 » Time-Sharing Parallel Applications with Performance Isolatio... |
103
Voted
DAC
2005
ACM
16 years 4 months ago
2005
ACM
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...
136
Voted
INFOCOM
2007
IEEE
15 years 9 months ago
2007
IEEE
— A deep understanding of the structural properties of wireless networks is critical for evaluating the performance of network protocols and improving their designs. Many protoco...
134
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INFOCOM
2005
IEEE
15 years 8 months ago
2005
IEEE
— This paper is about high capacity switches and routers that give guaranteed throughput, rate and delay guarantees. Many routers are built using input queueing or combined input...
106
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EUROPAR
1995
Springer
15 years 6 months ago
1995
Springer
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance ga...
126
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HPCA
2005
IEEE
16 years 3 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...