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119
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DDECS
2009
IEEE
106views Hardware» more  DDECS 2009»
15 years 9 months ago
Forward and backward guarding in early output logic
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
Charlie Brej, Doug Edwards
123
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HICSS
1998
IEEE
142views Biometrics» more  HICSS 1998»
15 years 6 months ago
Meetings in a Virtual Space: Creating a Digital Document
Improvements in computer network infrastructures and information utilities have led to an increase in the number of social and work interactions carried out `virtually' by ge...
Lori Toomey, Lia Adams, Elizabeth F. Churchill
128
Voted
TIME
2008
IEEE
15 years 9 months ago
Practical First-Order Temporal Reasoning
In this paper we consider the specification and verification of infinite-state systems using temporal logic. In particular, we describe parameterised systems using a new variet...
Clare Dixon, Michael Fisher, Boris Konev, Alexei L...
117
Voted
LCTRTS
2005
Springer
15 years 8 months ago
Transparent distribution of real-time components based on logical execution time
This paper introduces the notion of transparent distribution of real time software components. Transparent distribution means that (1) the functional and temporal behavior of a sy...
Emilia Farcas, Claudiu Farcas, Wolfgang Pree, Jose...
109
Voted
VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
16 years 3 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside