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119
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ET
2006
154views more  ET 2006»
15 years 3 months ago
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
Jack Smith, Tian Xia, Charles E. Stroud
IJNSEC
2006
112views more  IJNSEC 2006»
15 years 3 months ago
An Access Control System with Time-constraint Using Support Vector Machines
Access control is an important issue in information security. It is a necessary mechanism for protecting data in a computer system. In this paper, we apply support vector machines...
Chin-Chen Chang, Iuon-Chang Lin, Chia-Te Liao
101
Voted
IJON
2006
76views more  IJON 2006»
15 years 3 months ago
Joint maps for orientation, eye, and direction preference in a self-organizing model of V1
Primary visual cortex (V1) contains overlaid feature maps for orientation (OR), motion direction selectivity (DR), and ocular dominance (OD). Neurons in these maps are connected l...
James A. Bednar, Risto Miikkulainen
INTEGRATION
2006
102views more  INTEGRATION 2006»
15 years 3 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
GPEM
2007
95views more  GPEM 2007»
15 years 3 months ago
Where is evolutionary computation going? A temporal analysis of the EC community
Studying an evolving complex system and drawing some conclusions from it is an integral part of nature-inspired computing; being a part of that complex system, some insight can als...
Carlos Cotta, Juan Julián Merelo Guerv&oacu...