11328 search results - page 23 / 2266 » Timed Branching Processes |
104
Voted
ICCD
2006
IEEE
15 years 10 months ago
2006
IEEE
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
118
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ISCA
1999
IEEE
15 years 6 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
128
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CP
2005
Springer
15 years 7 months ago
2005
Springer
Abstract. Most CSP algorithms are based on refinements and extensions of backtracking, and employ one of two simple “branching schemes”: 2-way branching or d-way branching, fo...
143
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FPL
2003
Springer
15 years 7 months ago
2003
Springer
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating mo...
87
Voted
MICRO
2000
IEEE
15 years 6 months ago
2000
IEEE
Modern microprocessors employ increasingly complicated branch predictors to achieve instruction fetch bandwidth that is sufficient for wide out-of-order execution cores. While ex...