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ATS
2000
IEEE
134views Hardware» more  ATS 2000»
15 years 8 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
168
Voted
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
15 years 8 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...
IPPS
1999
IEEE
15 years 8 months ago
A Communication Latency Hiding Parallelization of a Traffic Flow Simulation
This work implements and analyses a highway traffic flow simulation based on continuum modeling of traffic dynamics. A traffic-flow simulation was developed and mapped onto a para...
Charles Michael Johnston, Anthony T. Chronopoulos
ECBS
2008
IEEE
116views Hardware» more  ECBS 2008»
15 years 10 months ago
CiCUTS: Combining System Execution Modeling Tools with Continuous Integration Environments
System execution modeling (SEM) tools provide an effective means to evaluate the quality of service (QoS) of enterprise distributed real-time and embedded (DRE) systems. SEM tools...
James H. Hill, Douglas C. Schmidt, Adam A. Porter,...
ISCAS
2003
IEEE
167views Hardware» more  ISCAS 2003»
15 years 9 months ago
The multi-level paradigm for distributed fault detection in networks with unreliable processors
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
Krishnaiyan Thulasiraman, Ming-Shan Su, V. Goel