4306 search results - page 537 / 862 » Timed Testing with TorX |
158
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ICFP
2002
ACM
16 years 4 months ago
2002
ACM
Compilers for dynamically and statically typed languages ensure safe execution by verifying that all operations are performed on appropriate values. An operation as simple as car ...
117
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FPGA
2010
ACM
15 years 11 months ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
140
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VLSI
2007
Springer
15 years 10 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
134
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
— A Parallel algorithm and its hardware implementation of Inverse Halftone operation is proposed in this paper. The algorithm is based on Lookup Tables from which the inverse hal...
155
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EMSOFT
2004
Springer
15 years 9 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...