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ICCD
1999
IEEE
91views Hardware» more  ICCD 1999»
15 years 8 months ago
Architectural Synthesis of Timed Asynchronous Systems
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
Brandon M. Bachman, Hao Zheng, Chris J. Myers
DAC
2003
ACM
16 years 5 months ago
Temporofunctional crosstalk noise analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H...
DLT
2003
15 years 5 months ago
NFA Reduction Algorithms by Means of Regular Inequalities
We present different techniques for reducing the number of states and transitions in nondeterministic automata. These techniques are based on the two preorders over the set of st...
Jean-Marc Champarnaud, Fabien Coulon
SAFECOMP
1998
Springer
15 years 8 months ago
Increasing System Safety for By-Wire Applications in Vehicles by Using a Time Triggered Architecture
By-wire systems have been established for several years in the area of aircraft construction and there are now approaches to utilize this technology in vehicles. The required elect...
Thomas Ringler, J. Steiner, R. Belschner, Bernd He...
CHARME
1993
Springer
68views Hardware» more  CHARME 1993»
15 years 8 months ago
Temporal Analysis of Time Bounded Digital Systems
To perform veri cation of digital systems with time bounded delays, it is essential to characterize the space of all possible system behaviors. In this paper, we describe our analy...
Alan R. Martello, Steven P. Levitan