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ISSS
2002
IEEE
106views Hardware» more  ISSS 2002»
15 years 2 months ago
Modeling Assembly Instruction Timing in Superscalar Architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...
SEKE
2005
Springer
15 years 3 months ago
Application of Design Combinatorial Theory to Scenario-Based Software Architecture Analysis
Design combinatorial theory for test-case generation has been used successfully in the past. It is useful in optimizing test cases as it is practically impossible to exhaustively t...
Chung-Horng Lung, Marzia Zaman
FDL
2007
IEEE
15 years 4 months ago
Time Modeling in MARTE
This article introduces the Time Model subprofile of MARTE, a new OMG UML Profile dedicated to Modeling and Analysis of Real-Time and Embedded systems. After a brief presentatio...
Robert de Simone, Charles André
CODES
2003
IEEE
15 years 3 months ago
Design optimization of mixed time/event-triggered distributed embedded systems
Distributed embedded systems implemented with mixed, eventtriggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases...
Traian Pop, Petru Eles, Zebo Peng
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
15 years 2 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...