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DATE
2010
IEEE
107views Hardware» more  DATE 2010»
15 years 2 months ago
Worst case delay analysis for memory interference in multicore systems
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...
Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia...
EMSOFT
2007
Springer
15 years 4 months ago
Loosely time-triggered architectures based on communication-by-sampling
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
Albert Benveniste, Paul Caspi, Marco Di Natale, Cl...
RTAS
2003
IEEE
15 years 3 months ago
Probabilistic Worst-Case Response-Time Analysis for the Controller Area Network
This paper presents a novel approach for calculating a probabilistic worst-case response-time for messages in the Controller Area Network (CAN). CAN uses a bit-stuffing mechanism...
Thomas Nolte, Hans Hansson, Christer Norström
RTAS
2005
IEEE
15 years 3 months ago
Feedback-Based Dynamic Voltage and Frequency Scaling for Memory-Bound Real-Time Applications
Dynamic voltage and frequency scaling is increasingly being used to reduce the energy requirements of embedded and real-time applications by exploiting idle CPU resources, while s...
Christian Poellabauer, Leo Singleton, Karsten Schw...
ENTCS
2006
145views more  ENTCS 2006»
14 years 9 months ago
A Classification of Time and/or Probability Dependent Security Properties
In multilevel systems it is important to avoid unwanted indirect information flow from higher levels to lower levels, namely the so called covert channels. Initial studnformation ...
Ruggero Lanotte, Andrea Maggiolo-Schettini, Angelo...