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CASES
2008
ACM
14 years 11 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....
EMSOFT
2006
Springer
15 years 1 months ago
New approach to architectural synthesis: incorporating QoS constraint
Embedded applications like video decoding, video streaming and those in the network domain, typically have a Quality of Service (QoS) requirement which needs to be met. Apart from...
Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan
RTCSA
2003
IEEE
15 years 3 months ago
Introducing Temporal Analyzability Late in the Lifecycle of Complex Real-Time Systems
Many industrial real-time systems have evolved over a long period of time and were initially so simple that it was possible to predict consequences of adding new functionality by c...
Anders Wall, Johan Andersson, Jonas Neander, Chris...
RTCSA
2006
IEEE
15 years 3 months ago
Algorithms for Determining the Demand-Based Load of a Sporadic Task System
The load parameter of a sporadic task system is defined to be the largest possible cumulative execution requirement that can be generated by jobs of the task system over any time...
Nathan Fisher, Theodore P. Baker, Sanjoy K. Baruah
CASES
2001
ACM
15 years 1 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder