660 search results - page 68 / 132 » Timed automata based analysis of embedded system architectur... |
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
—The paper presents architecture and synthesis results for an organic computing hardware for smart CMOS camera chips. The organic behavior in the chip hardware is based on distri...
LCTRTS
2009
Springer
15 years 4 months ago
2009
Springer
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
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RTCSA
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered Systemon-Chip (TTSoC) archi...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
DDECS
2007
IEEE
15 years 4 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...