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RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
15 years 3 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
FDL
2008
IEEE
15 years 4 months ago
Model-based Design Space Exploration for RTES with SysML and MARTE
The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Tim...
Marcello Mura, Luis Gabriel Murillo, Mauro Prevost...
ECRTS
2002
IEEE
15 years 2 months ago
Weakly Hard Real-time Constraints on Controller Area Network
For priority based buses such as CAN, worst case response time analysis is able to determine whether messages always meet their deadlines. This can include system models with boun...
Ian Broster, Guillem Bernat, Alan Burns
CEEMAS
2007
Springer
15 years 4 months ago
Simulating a Human Cooperative Problem Solving
Abstract. We are interested in understanding and simulating how humans elaborate plans in situations where knowledge is incomplete and how they interact to obtain missing informati...
Alexandre Pauchet, Amal El Fallah-Seghrouchni, Nat...
RTAS
2011
IEEE
14 years 1 months ago
End-to-End Delay Analysis for Fixed Priority Scheduling in WirelessHART Networks
—The WirelessHART standard has been specifically designed for real-time communication between sensor and actuator devices for industrial process monitoring and control. End-toen...
Abusayeed Saifullah, You Xu, Chenyang Lu, Yixin Ch...