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ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
15 years 3 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
IJCAI
1993
14 years 11 months ago
A Model-Theoretic Approach to the Verification of Situated Reasoning Systems
agent-oriented system. We show the complexity to be linear time for one of these logics and polynomial time for another, thus providing encouraging results with respect to the prac...
Anand S. Rao, Michael P. Georgeff
HICSS
2000
IEEE
124views Biometrics» more  HICSS 2000»
15 years 1 months ago
An Empirical Study of Distribution based on Voyager: A Performance Analysis
The paper describes the model, implementation and experimental evaluation of a distributed Kohonen Neural Network application (Kohonen Application). The aim of this research is to...
Sérgio Viademonte, Frada Burstein, Fá...
DAC
2006
ACM
15 years 10 months ago
Fast analysis of structured power grid by triangularization based structure preserving model order reduction
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
Hao Yu, Yiyu Shi, Lei He
IMC
2003
ACM
15 years 3 months ago
Virtual landmarks for the internet
Internet coordinate schemes have been proposed as a method for estimating minimum round trip time between hosts without direct measurement. In such a scheme, each host is assigned...
Liying Tang, Mark Crovella