395 search results - page 12 / 79 » Timed circuits: a new paradigm for high-speed design |
123
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ICCAD
1999
IEEE
15 years 6 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
102
Voted
ICCAD
1999
IEEE
15 years 6 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
113
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CAV
1994
Springer
15 years 6 months ago
1994
Springer
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
117
Voted
TCAD
1998
15 years 1 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
108
Voted
ICCAD
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract— Chip-package thermal analysis is necessary for the design and synthesis of reliable, high-performance, low-power, compact integrated circuits (ICs). Many methods of IC ...