395 search results - page 13 / 79 » Timed circuits: a new paradigm for high-speed design |
114
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DAC
2005
ACM
16 years 2 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
120
Voted
ACSD
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion...
89
Voted
CORR
2007
Springer
15 years 1 months ago
2007
Springer
: New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology’s scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristi...
ASPDAC
1998
ACM
15 years 6 months ago
1998
ACM
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...
106
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DAC
2005
ACM
15 years 3 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...