395 search results - page 17 / 79 » Timed circuits: a new paradigm for high-speed design |
107
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DAC
2006
ACM
16 years 2 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
131
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BROADNETS
2006
IEEE
15 years 5 months ago
2006
IEEE
Traffic grooming continues to be a rich area of research in the context of WDM optical networks. We provide an overview of the optical and electronic grooming techniques available...
126
Voted
TVLSI
1998
15 years 1 months ago
1998
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
92
Voted
ISCAS
2006
IEEE
15 years 8 months ago
2006
IEEE
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
121
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DAC
2004
ACM
16 years 2 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...