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» Timed circuits: a new paradigm for high-speed design
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ACMSE
2005
ACM
15 years 7 months ago
The bipartite clique: a topological paradigm for WWWeb user search customization
Web user search customization research has been fueled by the recognition that if the WWW is to attain to its optimal potential as an interactive medium the development of new and...
Brenda F. Miles, Vir V. Phoha
FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
15 years 7 months ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 7 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
MICRO
2002
IEEE
156views Hardware» more  MICRO 2002»
15 years 1 months ago
TCP Switching: Exposing Circuits to IP
There has been much discussion about the best way to combine the benefits of new optical circuit switching technology with the established packet switched Internet. In this paper,...
Pablo Molinero-Fernández, Nick McKeown
JETC
2008
127views more  JETC 2008»
15 years 12 days ago
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
Yong Zhan, Sachin S. Sapatnekar