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» Timed circuits: a new paradigm for high-speed design
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115
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IPPS
2005
IEEE
15 years 7 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
GECCO
2006
Springer
143views Optimization» more  GECCO 2006»
15 years 5 months ago
A hybridized genetic parallel programming based logic circuit synthesizer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
Wai Shing Lau, Kin-Hong Lee, Kwong-Sak Leung
CHES
2010
Springer
187views Cryptology» more  CHES 2010»
15 years 3 months ago
Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs - (Full Version)
The power of side-channel leakage attacks on cryptographic implementations is evident. Today's practical defenses are typically attack-specific countermeasures against certain...
Kimmo Järvinen, Vladimir Kolesnikov, Ahmad-Re...
ISPD
2009
ACM
112views Hardware» more  ISPD 2009»
15 years 8 months ago
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
The multiple-supply voltage (MSV) design style has been extensively applied to mitigate dynamic-power consumption. The MSV design paradigm, however, brings many crucial challenges...
Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang
109
Voted
INTEGRATION
2008
87views more  INTEGRATION 2008»
15 years 1 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco