395 search results - page 21 / 79 » Timed circuits: a new paradigm for high-speed design |
115
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RTCSA
2005
IEEE
15 years 7 months ago
2005
IEEE
We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a...
DAC
2002
ACM
16 years 2 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
236
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GLVLSI
2011
IEEE
14 years 5 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
116
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ICCAD
1994
IEEE
15 years 6 months ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
100
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ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...