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» Timed circuits: a new paradigm for high-speed design
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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
15 years 10 months ago
A Probabilistic-Based Design Methodology for Nanoscale Computation
As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research p...
R. Iris Bahar, Joseph L. Mundy, Jie Chen
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
15 years 7 months ago
Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing
The nature of IC design has is necessarily evolving to a more data-centric design flow in which EDA tools share a common information in a design database without the negative cost...
D. R. Cottrell, T. J. Grebinski
DAC
2005
ACM
15 years 3 months ago
On the need for statistical timing analysis
Traditional corner analysis fails to guarantee a target yield for a given performance metric. However, recently proposed solutions, in the form of statistical timing analysis, whi...
Farid N. Najm
MJ
2007
119views more  MJ 2007»
15 years 1 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
CSREAESA
2006
15 years 3 months ago
Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy
- Triple Modular Redundancy is widely used in dependable systems design to ensure high reliability against soft errors. Conventional TMR is effective in protecting sequential circu...
Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wan...