395 search results - page 25 / 79 » Timed circuits: a new paradigm for high-speed design |
130
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TVLSI
2010
14 years 8 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
107
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ASPDAC
2006
ACM
15 years 8 months ago
2006
ACM
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...
VLSI
2010
Springer
15 years 8 days ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
120
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COMPGEOM
1997
ACM
15 years 6 months ago
1997
ACM
Abstract. In the context of methodologies intended to confer robustness to geometric algorithms, we elaborate on the exact-computation paradigm and formalize the notion of degree o...
111
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DAC
1997
ACM
15 years 6 months ago
1997
ACM
In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergra...