395 search results - page 28 / 79 » Timed circuits: a new paradigm for high-speed design |
178
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ISPD
2012
ACM
13 years 9 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
110
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FPL
2005
Springer
15 years 7 months ago
2005
Springer
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
125
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DAC
2007
ACM
16 years 2 months ago
2007
ACM
Abstract-- The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and ca...
127
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GI
2004
Springer
15 years 7 months ago
2004
Springer
: The transition from microelectronics to nanoelectronics reaches physical limits and results in a paradigm shift in the design and fabrication of electronic circuits. The conserva...
119
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DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...