395 search results - page 30 / 79 » Timed circuits: a new paradigm for high-speed design |
104
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ATS
2005
IEEE
15 years 7 months ago
2005
IEEE
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
107
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DAC
2003
ACM
16 years 2 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
113
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DDECS
2009
IEEE
15 years 8 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
144
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CASES
2010
ACM
14 years 12 months ago
2010
ACM
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
129
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GI
2009
Springer
15 years 6 months ago
2009
Springer
: Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets)...