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COLT
2006
Springer
15 years 5 months ago
Efficient Learning Algorithms Yield Circuit Lower Bounds
We describe a new approach for understanding the difficulty of designing efficient learning algorithms. We prove that the existence of an efficient learning algorithm for a circui...
Lance Fortnow, Adam R. Klivans
SDL
2003
147views Hardware» more  SDL 2003»
15 years 3 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
ASPDAC
1998
ACM
101views Hardware» more  ASPDAC 1998»
15 years 6 months ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
Jinan Lou, Amir H. Salek, Massoud Pedram
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
15 years 6 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
ISVLSI
2006
IEEE
77views VLSI» more  ISVLSI 2006»
15 years 8 months ago
A Robust Synchronizer
We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can mor...
Jun Zhou, David Kinniment, Gordon Russell, Alexand...