Sciweavers

395 search results - page 36 / 79
» Timed circuits: a new paradigm for high-speed design
Sort
View
DAC
2005
ACM
15 years 3 months ago
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
115
Voted
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
15 years 10 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 5 months ago
Battery-aware code partitioning for a text to speech system
The advent of multi-core embedded processors has brought along new challenges for embedded system design. This paper presents an efficient, battery aware, code partitioning techni...
Anirban Lahiri, Anupam Basu, Monojit Choudhury, Sr...
CCE
2007
15 years 3 months ago
A Web Services based Approach for System on a Chip Design Planning
: The concept of Virtual Organisation (VO) offers various solutions to management, collaboration and coordination issues important for distributed collaborating teams. Deployment o...
Maciej Witczynski, Edward Hrynkiewicz, Adam Pawlak
ICCD
2005
IEEE
224views Hardware» more  ICCD 2005»
15 years 11 months ago
Algorithmic and Architectural Design Methodology for Particle Filters in Hardware
In this paper we present algorithmic and architectural methodology for building Particle Filters in hardware. Particle filtering is a new paradigm for filtering in presence of n...
Aswin C. Sankaranarayanan, Rama Chellappa, Ankur S...