395 search results - page 48 / 79 » Timed circuits: a new paradigm for high-speed design |
133
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FPGA
2004
ACM
15 years 7 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
122
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CASES
2009
ACM
15 years 6 months ago
2009
ACM
Nanowire crossbar circuits are an emerging architectural paradigm that promises a higher integration density and an improved fault-tolerance due to its reconfigurability. In this...
114
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DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
ICASSP
2008
IEEE
15 years 8 months ago
2008
IEEE
A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative Message Passing (iMP) to be run on loopy...
148
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RTAS
2008
IEEE
15 years 8 months ago
2008
IEEE
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...