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» Timed circuits: a new paradigm for high-speed design
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VLDB
2007
ACM
198views Database» more  VLDB 2007»
16 years 2 months ago
The End of an Architectural Era (It's Time for a Complete Rewrite)
In previous papers [SC05, SBC+07], some of us predicted the end of "one size fits all" as a commercial relational DBMS paradigm. These papers presented reasons and exper...
Michael Stonebraker, Samuel Madden, Daniel J. Abad...
DAC
2003
ACM
16 years 2 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
15 years 7 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
TCOM
2010
106views more  TCOM 2010»
15 years 9 days ago
On the system level prediction of joint time frequency spreading systems with carrier phase noise
- Phase noise is a topic of theoretical and practical interest in electronic circuits. Although progress has been made in the characterization of its description, there are still c...
Youssef Nasser, Mathieu Des Noes, Laurent Ros, Gen...
ECCV
2010
Springer
14 years 11 months ago
An Efficient Graph Cut Algorithm for Computer Vision Problems
Abstract. Graph cuts has emerged as a preferred method to solve a class of energy minimization problems in computer vision. It has been shown that graph cut algorithms designed kee...
Chetan Arora, Subhashis Banerjee, Prem Kalra, S. N...