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» Timed circuits: a new paradigm for high-speed design
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DATE
2003
IEEE
124views Hardware» more  DATE 2003»
15 years 7 months ago
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...
Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, Ting...
DAC
2001
ACM
16 years 2 months ago
An Algorithm for Bi-Decomposition of Logic Functions
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
Alan Mishchenko, Bernd Steinbach, Marek A. Perkows...
FDL
2003
IEEE
15 years 7 months ago
Using Symbolic Simulation for Bounded Property Checking
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
Jürgen Ruf, Prakash Mohan Peranandam, Thomas ...
FPL
2009
Springer
179views Hardware» more  FPL 2009»
15 years 5 months ago
Building heterogeneous reconfigurable systems using threads
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
Jason Agron, David L. Andrews
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
15 years 6 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...