395 search results - page 55 / 79 » Timed circuits: a new paradigm for high-speed design |
101
click to vote
DAC
2006
ACM
16 years 2 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
DATE
2010
IEEE
15 years 7 months ago
2010
IEEE
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
112
click to vote
ISCAS
2007
IEEE
15 years 8 months ago
2007
IEEE
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...
113
click to vote
ASPDAC
2005
ACM
15 years 7 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
103
click to vote
ISPD
2003
ACM
15 years 7 months ago
2003
ACM
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved i...