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» Timed circuits: a new paradigm for high-speed design
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DAC
2008
ACM
16 years 2 months ago
Path smoothing via discrete optimization
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can als...
Michael D. Moffitt, David A. Papa, Zhuo Li, Charle...
ASPDAC
2007
ACM
129views Hardware» more  ASPDAC 2007»
15 years 6 months ago
ECO-system: Embracing the Change in Placement
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
Jarrod A. Roy, Igor L. Markov
DAC
2010
ACM
14 years 12 months ago
A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs
The verification of large radio-frequency/millimeter-wave (RF/MM) integrated circuits (ICs) has regained attention for high-performance designs beyond 90nm and 60GHz. The traditio...
Xuexin Liu, Hao Yu, Sheldon X.-D. Tan
DAC
2004
ACM
16 years 2 months ago
Exploiting structure in symmetry detection for CNF
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
16 years 2 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy