395 search results - page 60 / 79 » Timed circuits: a new paradigm for high-speed design |
110
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VTS
2007
IEEE
15 years 8 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
87
Voted
FPL
2005
Springer
15 years 7 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
INFOCOM
2009
IEEE
15 years 8 months ago
2009
IEEE
—The recently proposed Pocket Switched Network paradigm takes advantage of human social contacts to opportunistically create data paths over time. We examine how effective such a...
146
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DAC
2004
ACM
16 years 2 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...