395 search results - page 61 / 79 » Timed circuits: a new paradigm for high-speed design |
VLSID
2004
IEEE
16 years 2 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
145
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DAC
2004
ACM
15 years 5 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
129
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ENTCS
2008
15 years 1 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
127
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JGAA
2006
15 years 1 months ago
2006
Visualization of circuits is an important research area in electronic design automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses or...
119
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CISS
2008
IEEE
15 years 8 months ago
2008
IEEE
Abstract—Cross-layer optimization including congestion control, routing, and scheduling has shown dramatic throughput improvement over layered designs for wireless networks. In p...