395 search results - page 63 / 79 » Timed circuits: a new paradigm for high-speed design |
142
Voted
ISSS
2000
IEEE
15 years 6 months ago
2000
IEEE
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
105
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GLVLSI
2005
IEEE
15 years 7 months ago
2005
IEEE
We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the ...
128
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ISPD
2010
ACM
15 years 8 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
155
Voted
CODES
2003
IEEE
15 years 7 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
104
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ISPD
2003
ACM
15 years 7 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...