395 search results - page 67 / 79 » Timed circuits: a new paradigm for high-speed design |
104
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DAC
2005
ACM
15 years 3 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
127
Voted
TECS
2008
15 years 1 months ago
2008
straction SUDEEP PASRICHA and NIKIL DUTT University of California, Irvine and MOHAMED BEN-ROMDHANE Newport Media Inc. Currently, system-on-chip (SoC) designs are becoming increasin...
120
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MOBIHOC
2006
ACM
16 years 1 months ago
2006
ACM
Traditionally, ad hoc networks have been viewed as a connected graph over which end-to-end routing paths had to be established. Mobility was considered a necessary evil that inval...
127
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DAC
2003
ACM
16 years 2 months ago
2003
ACM
Skin effect makes interconnect resistance and inductance frequency dependent. This paper addresses the problem of efficiently estimating the signal characteristics of any RLC netw...
113
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ISPD
2003
ACM
15 years 7 months ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...