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» Timed circuits: a new paradigm for high-speed design
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99
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ASPDAC
2007
ACM
77views Hardware» more  ASPDAC 2007»
15 years 5 months ago
Hippocrates: First-Do-No-Harm Detailed Placement
Physical synthesis optimizations and engineering change orders typically change the locations of cells, resize cells or add more cells to the design after global placement. Unfort...
Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-J...
167
Voted
DAC
2006
ACM
16 years 2 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
ISCAS
2006
IEEE
88views Hardware» more  ISCAS 2006»
15 years 8 months ago
SiP integration of intelligent, adaptive, self-sustaining power management solutions for portable applications
Abstract—Power management is an essential component of any electrical system, and nowadays a limiting factor in the miniaturization of portable electronic devices. Not only are t...
E. O. Torres, Min Chen, H. Pooya Forghani-zadeh, V...
DATE
2007
IEEE
148views Hardware» more  DATE 2007»
15 years 8 months ago
Temperature aware task scheduling in MPSoCs
In deep submicron circuits, elevation in temperatures has brought new challenges in reliability, timing, performance, cooling costs and leakage power. Conventional thermal managem...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...
118
Voted
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
15 years 6 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...