395 search results - page 74 / 79 » Timed circuits: a new paradigm for high-speed design |
128
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DAC
2010
ACM
15 years 3 months ago
2010
ACM
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
116
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ICCAD
1997
IEEE
15 years 4 months ago
1997
IEEE
We introduce a new technique to solve exactly a discrete optimization problem, based on the paradigm of “negative” thinking. The motivation is that when searching the space of...
109
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WSC
1998
15 years 1 months ago
1998
The High Level Architecture (HLA) for distributed simulations was proposed by the Defense Modeling and Simulation Office of the Department of Defense (DOD) in order to support int...
102
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DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—This paper reports on experience gained and lessons learned from an intensive investigation of model-driven engineering methodology and technology for application to high-integr...
DAC
2006
ACM
16 years 21 days ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...