395 search results - page 8 / 79 » Timed circuits: a new paradigm for high-speed design |
109
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DAC
2006
ACM
16 years 21 days ago
2006
ACM
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
DELTA
2002
IEEE
15 years 4 months ago
2002
IEEE
Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry...
111
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ISLPED
2007
ACM
15 years 1 months ago
2007
ACM
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
112
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TVLSI
2008
14 years 11 months ago
2008
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
105
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PAM
2012
Springer
13 years 7 months ago
2012
Springer
Network administrators are faced with the increasingly challenging task of monitoring their network’s health in real time, drawing upon diverse and voluminous measurement data fe...