395 search results - page 9 / 79 » Timed circuits: a new paradigm for high-speed design |
112
Voted
ITC
2003
IEEE
15 years 7 months ago
2003
IEEE
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus pr...
123
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SAC
2006
ACM
15 years 7 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
98
Voted
DAC
2005
ACM
16 years 2 months ago
2005
ACM
A rational Arnoldi method for passivity-preserving model-order reduction (MOR) with implicit multi-point moment matching for systems with frequency-dependent interconnects is desc...
120
Voted
DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
118
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EURODAC
1994
IEEE
15 years 6 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...