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CODES
2008
IEEE
15 years 11 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
VEE
2012
ACM
269views Virtualization» more  VEE 2012»
14 years 10 hour ago
SimTester: a controllable and observable testing framework for embedded systems
In software for embedded systems, the frequent use of interrupts for timing, sensing, and I/O processing can cause concurrency faults to occur due to interactions between applicat...
Tingting Yu, Witawas Srisa-an, Gregg Rothermel
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
15 years 6 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...
PASTE
2004
ACM
15 years 10 months ago
Validation of assembler programs for DSPs: a static analyzer
Digital Signal Processors are widely used in critical embedded systems to pilot low-level, often critical functionalities. We describe a static analyzer based on abstract interpre...
Matthieu Martel
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 9 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita