40 search results - page 4 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
102
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VLSID
2002
IEEE
15 years 2 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
A new partitioningapproach for very largecircuits is described. We demonstrate that applying a recently developed analytical placement algorithm, that pro ts from a linear objecti...
DAC
2003
ACM
15 years 2 months ago
2003
ACM
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
71
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ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...