40 search results - page 6 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
ISPD
2004
ACM
13 years 11 months ago
2004
ACM
Many current designs contain a large number of standard cells intermixed with larger macro blocks. The range of size in these “mixed block” designs complicates the placement p...
FPL
2005
Springer
13 years 11 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
DATE
2008
IEEE
14 years 20 days ago
2008
IEEE
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
ASPDAC
2000
ACM
13 years 10 months ago
2000
ACM
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...