28 search results - page 2 / 6 » Timing Driven Placement for Quasi Delay-Insensitive Circuits |
78
Voted
DAC
1995
ACM
15 years 3 months ago
1995
ACM
93
Voted
ICCAD
2001
IEEE
15 years 9 months ago
2001
IEEE
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
89
Voted
FPL
2004
Springer
15 years 5 months ago
2004
Springer
Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement s...
94
Voted
ICCAD
1995
IEEE
15 years 3 months ago
1995
IEEE
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
84
Voted
DAC
2006
ACM
16 years 1 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...