72 search results - page 15 / 15 » Timing Optimization of Logic Network Using Gate Duplication |
135
Voted
CF
2006
ACM
15 years 4 months ago
2006
ACM
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
124
Voted
ICCAD
2003
IEEE
15 years 10 months ago
2003
IEEE
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...